1. Field of the Invention
The present invention relates to a display unit such as a capacitive flat matrix display (referred to as a thin film EL display hereinafter) or a plasma display.
2. Description of the Prior Art
FIG. 6 is a block diagram showing a structure of a common thin film EL display unit.
A display panel 1 is formed of a thin film EL element. In the thin film EL element, belt-shaped transparent electrodes are arranged in parallel on a glass substrate, a three-layer structure is formed by laminating a dielectric material, an EL layer, thereon and the dielectric material thereon and then arranging belt-shaped back electrodes in parallel in a direction crossing at a right angle to the transparent electrodes. The thin film El element is driven by a comparatively high voltage of approximately 200 V as is apparent from an applied voltage-brightness characteristic graph shown in FIG. 7.
In the display panel 1, the transparent electrodes of the thin film EL element are designated by data side electrodes D1 to Dm and the back electrodes of the thin film EL element are designated by scanning side electrodes S1 to Sn.
A data side switching circuit 2 is a circuit for individually applying a modulation voltage VM to each of data side electrodes D1 to Dm. The circuit comprises a data side output port group 3 connected to each of the data side electrodes D1 to Dm and a logical circuit 4 which receives display data corresponding to each of the data side electrodes D1 to Dm and turns the data side output port group 3 on and off in accordance with the display data.
A scanning side switching circuit 5 is a circuit for sequentially applying writing voltages VW1 and -VW2 (VW1=VW2+VM) to the scanning side electrodes S1 to Sn in order. The circuit comprises a scanning side output port group 6 connected to each of the scanning side electrodes S1 to Sn and a logical circuit 7 which turns the scanning side output port group 6 on and off in accordance with the order of the scanning side electrodes S1 to Sn.
A drive circuit 8 is a circuit for generating a high voltage for driving the display panel 1 from a constant reference voltage VD. The circuit comprises a modulation drive circuit 9 for applying the modulation voltage VM to the data side output port group 3 and a writing drive circuit 10 for applying the writing voltages VW1 and -VW2 to the scanning side output port group 6.
A driving logical circuit 11 is a circuit for generating various timing signals necessary for drive of the display panel 1 in accordance with an input signal such as display data D, a data transfer clock CK, a horizontal synchronizing signal H or a vertical synchronizing signal V.
Fundamental drive of the display unit, in which a period over two first and second fields is one cycle, is performed by applying the modulation voltage VM corresponding to the display data which decides emission or non-emission, to the data side electrodes D1 to Dm, while applying the voltage VW1 in the first field and the voltage -VW2 in the second field as the writing voltage to the scanning side electrodes S1 to Sn in order.
By this display drive, a superimposed effect or an offset effect of the writing voltages VW1, -VW2 and the modulation voltage VM is generated at a pixel where the data side electrodes D1 to Dm and the scanning side electrodes S1 to Sn cross. As the thin film EL element forming the display panel 1 shows the applied voltage-brightness characteristic shown in FIG. 7, the voltage VW1 of an emission threshold voltage Vth or more or the voltage VW2 of the emission threshold voltage Vth or less is applied to the pixel as an effective voltage by the superimposed effect and the offset effect of the writing voltages VW1, -VW2 and the modulation voltage VM. Thus, each pixel becomes either an emission or non-emission state and then a predetermined display can be obtained.
Therefore, the effective voltage whose polarity is inverted is alternatively applied to one pixel in the first and second fields, whereby symmetrical AC drive, which is ideal for the thin film EL element, can be performed in the two fields of one cycle.
FIG. 8 is a block diagram showing a structure of the writing drive circuit 10 and the driving logical circuit 11 in detail. The writing drive circuit 10 comprises a high voltage power supply 13 which generates a high voltage HV and a switching element 12 for obtaining pulse-shaped writing voltages VW1 and VW2 which correspond to the timing when the scanning side output port group 6 specifies the row of each pixel in the display panel 1 by intermittently supplying the high voltage HV to the scanning side output port group 6. On and off of the switching element 12 is controlled by a control signal HVC from the driving logical circuit 11.
In addition, the driving logical circuit 11 comprises a memory 14 such as a read only memory and the control signal HVC is output in accordance with the timing written in the memory 14.
FIG. 9 shows timing charts illustrating the timing of the drive of the display unit, in which FIG. 9(1) shows a vertical synchronizing signal V. FIG. 9(2) shows a pulse waveform of the writing voltage applied to the scanning side electrodes S1 to Sn; and FIG. 9(3) shows a waveform of the high voltage HV output from the high voltage power supply 13 in the writing drive circuit 10.
According to the conventional display unit, there is fluctuation in the high voltage HV output from the high voltage power supply 13 in the writing drive circuit 10 as shown in FIG. 9. Therefore, the amplitude of the pulse voltage applied as the writing voltages Vw1 and -Vw2 varies according to the scanning side electrode. As a result, a brightness difference is generated between scanning lines on a screen, causing display quality to be considerably deteriorated.
More specifically, as shown in FIG. 9(1), after the writing voltage is applied to the last scanning side electrode Sn, there is a blank period in the vertical synchronizing signal V before it is applied to the first scanning side electrode S1 in the next field. For this period a load to the high voltage power supply 13 is decreased and then an output level of the high voltage power supply 13 is increased as shown in FIG. 9(3). Thus, even if the writing voltage starts to be applied to the scanning side electrode S1, the output level does not immediately return to a predetermined value and the output level is kept high for a while. As a result, the writing voltage applied to the first scanning side electrode S1 is higher than that applied to the last scanning side electrode Sn, so that a brightness difference between the scanning lines is generated.
As means for solving the above problems, it is thought that load fluctuation of the high voltage power supply 13 itself should be held down. However, in this case, it is necessary to insert a large capacity capacitor into an output stage of the high voltage power supply 13 or increase control precision of the control circuit for the high voltage power supply 13, causing an increase of the number of parts, which in turn causes an increase in cost.